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rev.1.0 apr 20, 2004 page 1 of 21 hd49340np/hnp cds/pga & 10-bit a/d converter rej03f0109-0100z rev.1.0 apr 20, 2004 description the hd49340np/hnp is a cmos ic that provides cds-pga analog processing (cds/pga) suitable for ccd camera digital signal processing systems together with a 10-bit a/d converter in a single chip. functions ? correlated double sampling ? pga ? offset compensation ? serial interface control ? 10-bit adc ? operates using only the 3 v voltage ? corresponds to switching mode of power dissipation and operating frequency power dissipation: 120 mw (typ), maximum frequency: 36 mhz (hd49340hnp) power dissipation: 60 mw (typ), maximum frequency: 25 mhz (hd49340np) ? adc direct input mode ? qfn 36-pin package features ? suppresses low-frequency noise output from ccd by the s/h type correlated double sampling. ? the s/h response frequency characteristics for the reference level can be adjusted using values of external parts and registers. ? high sensitivity is achieved due to the high s/n ratio and a wide coverage provided by a pg amplifier. ? feedback is used to compensate and reduce the dc offsets including the output dc offset due to pga gain change and the ccd offset in the cds (correlated double sampling) amplifier input. ? pga, standby mode, etc., is achieved via a serial interface. ? high precision is provided by a 10-bit-resolution a/d converter.
hd49340np/hnp rev.1.0 apr 20, 2004 page 2 of 21 pin arrangement adcin av ss av dd bias blkc cdsin blkfb blksh av dd d1 d2 d3 d4 d5 d6 d7 d8 d9 27 26 25 24 23 22 21 20 19 123456789 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 (top view) av ss spsig spblk obp pblk dv dd adclk dv ss drdv dd vrm vrt vrb dv dd dv ss cs sdata sck d0 pin description pin no. symbol description i/o analog(a) or digital(d) 1 to 9 d0 to d9 digital output o d 10 drdv dd output buffer power supply (3 v) ? d 11 dv ss digital ground (0 v) ? d 12 adclk adc conversion clock input pin i d 13 dv dd digital power supply (3 v) ? d 14 pblk preblanking input pin i d 15 obp optical black pulse input pin i d 16 spblk black level sampling clock input pin i d 17 spsig signal level sampling clock input pin i d 18 av ss analog ground (0 v) ? a 19 av dd analog power supply (3 v) ? a 20 blksh black level s/h pin ? a 21 blkfb black level fb pin ? a 22 cdsin cds input pin i a 23 blkc black level c pin ? a 24 bias internal bias pin connect a 33 k ? resistor between bias and av ss . ? a 25 av dd analog power supply (3 v) ? a 26 av ss analog ground (0 v) ? a 27 adcin adc input pin ? a 28 vrm reference voltage pin 1 connect a 0.1 f ceramic capacitor between vrm and av ss . ? a 29 vrt reference voltage pin 3 connect a 0.1 f ceramic capacitor between vrt and av ss . ? a 30 vrb reference voltage pin 2 connect a 0.1 f ceramic capacitor between vrb and av ss . ? a
hd49340np/hnp rev.1.0 apr 20, 2004 page 3 of 21 pin description (cont.) pin no. symbol description i/o analog(a) or digital(d) 31 dv dd digital power supply (3 v) ? d 32 dv ss digital ground (0 v) ? d 33 cs serial interface control input pin i d 34 sdata serial data input pin i d 35 sck serial clock input pin i d 36 d0 digital output o d note: 1. with pull-down resistor. input/output equivalent circuit pin name equivalent circuit digital output d0 to d9 din dv dd stby digital output digital input adclk, obp, spblk, spsig, cs, sck, sdata, pblk digital input dv dd cdsin cdsin internally connected to vrt av dd adcin a dcin internally connected to vrm av dd blksh, blkfb, blkc blkfb av dd blksh blkc ? + vrt, vrm, vrb ? + ? + ? + vrt vrb av dd vrm analog bias bias av dd
hd49340np/hnp rev.1.0 apr 20, 2004 page 4 of 21 block diagram 33 34 32 43 45 44 17 27 26 28 29 35 2 3 4 5 6 7 8 42 9 19 18 16 31 10bit adc oeb vrb vrm vrt obp adcin cdsin cds pga blksh 26 pblk 28 blkc d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 blkfb cs sdata sck bias timing generator 19 18 16 adclk spblk spsig dv dd drdv dd av ss av dd 19 dv ss dc offset compensation circuit serial interface bias generator output latch circuit
hd49340np/hnp rev.1.0 apr 20, 2004 page 5 of 21 internal functions functional description ? cds input ? ccd low-frequency noise is suppressed by cds (correlated double sampling). ? the signal level is clamped at 14 lsb to 76 lsb by resister during the ob period. * 1 ? gain can be adjusted using 8 bits of register (0.132 db steps) within the range from ?2.36 db to 31.40 db. * 2 ? adc input ? the center level of the input signal is clamped at 512 lsb (typ). ? gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (?4.86 db) to 5.14 times (14.22 db). * 1 ? automatic offset calibration of pga and adc ? dc offset compensation feedback for ccd and cds ? pre-blanking ? cds input operation is protected by separating it from the large input signal. ? digital output is set at clamp level by resister. ? digital output enable function notes: 1. it is not covered by warranty when 14lsb settings 2. full-scale digital output is defined as 0 db (one time) when 1 v is input. operating description figure 1 shows cds/pga + adc function block. gain setting (register) clamp data (register) d0 to d9 dac c3 cds amp pg amp cdsin blkfb blksh sh amp adcin c2 c1 vrt 10bit adc blkc c4 obp offset calibration logic dc offset feedback logic current dac figure 1 hd49340np/hnp functional block diagram 1. cds (correlated double sampling) circuit the cds circuit extracts the voltage differential between th e black level and a signal including the black level. the black level is directly sampled at c1 by using the spbl k pulse, buffered by the shamp, then provided to the cdsamp. the signal level is directly sampled at c2 by using the spsig pulse, and provided to cdsamp (see figure 1). the difference between these two signal levels is extracted by the cdsamp, which also operates as a programmable gain amplifier at the previous stage. the cds input is biased with vrt (2 v) during the spblk pulse validation period. during the pblk period, the above sampling and bias operation are paused.
hd49340np/hnp rev.1.0 apr 20, 2004 page 6 of 21 2. pga circuit the pgamp is the programmable gain amplifier for the latter stage. the pgamp and the cdsamp set the gain using 8 bits of register. the equation below shows how the gain changes when register value n is from 0 to 255. in cdsin mode: gain = (?2.36 db + 0.132 db) n (log linear). in adcin mode: gain = (0.57 times + 0.00446 times) n (linear). full-scale digital output is defined as 0 db (one time) when 1 v is input. 3. automatic offset calibration function and black-level clamp data setting the dac dc voltage added to the output of the pgamp is adjusted by automatic offset calibration. the data, which cancels the output offset of the pgamp and the input offset of the adc, and the clamp data (14 lsb to 76 lsb) set by register are added and input to the dac. the automatic offset calibration starts automatically after the reset mode set by register 1 is cancelled and terminates after 40000 clock cycles (when fclk = 20 mhz, 2 ms). 4. dc offset compensation feedback function feedback is done to set the black signal level input during the ob period to the dc standard, and all offsets (including the ccd offset and the cdsamp offset) are compensated for. the offset from the adc output is calculated during the ob period, and shamp feedback capacitor c3 is charged by the current dac (see figure 1). the open-loop differential gain ( ? gain/ ? h) per 1 h of the feedback loop is given by the following equation. 1h is the one cycle of the obp. ? gain/ ? h = 0.078/(fclk c3) (fclk: adclk frequency, c3: shamp external feedback capacitor) example: when fclk = 20 mhz and c3 = 1.0 f, ? gain/ ? h = 0.0039 when the pgamp gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop gain is increased by a multiple of n. loop gain multiplication factor n can be selected from 4 times, 8 times, 16 times, or 32 times by changing the register settings (see table 1). note that the open-loop differential gain ( ? gain/ ? h) must be one or lower. if it is two or more, oscillation occurs. the time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be selected from 1 h, 2 h, 4 h, or 8 h. if the offset error is over 32 lsb, the high-speed lead-in operation continues, and when the offset error is 32 lsb or less, the operation returns to the normal loop-gain operation after 1 h, 2 h, 4 h, or 8 h depending on the register settings. see table 2. table 1 loop gain multiplication factor during high-speed lead-in operation table 2 high-speed lead-in operation cancellation time hgain-nsel (register settings) multiplication factor n hgstop-hsel (register settings) cancellation time [0] l h l h [1] l h h l 4 32 16 8 [0] l h l h [1] l h h l 1 h 8 h 4 h 2 h 5. pre-blanking function during the pblk input period, the cds input operation is separated and protected from the large input signal. the adc digital output is fixed to clamp data (14 to 76 lsb).
hd49340np/hnp rev.1.0 apr 20, 2004 page 7 of 21 6. adc digital output control function the adc digital output includes the functions output enable, code conversion, and test mode. tables 3, 4 and 5 show the output functions and the codes. table 3 adc digital output functions notes: 1. stby, test, linv, and minv are set by register. 2. mode setting for the pblk is done by external input pins. 3. the polarity of the pblk pin when the register setting is spinv is low. h l h l l l h h h h l l l l h h h h l l l l h h h h l l l l h h h h l l l l h h x h h h h l h h h h l x x x x x l h l h x l h l h x l h l h x l l h h x l l h h x l l h h x l h x x l h h l stby d9 test0 operating mode adc digital output d0 d1 d2 d3 d4 d5 d6 d7 d8 pblk minv test1 linv hi-z same as in table 4. d9 is inverted in table 4. d8 to d0 are inverted in table 4. d9 to d0 are inverted in table 4. output code is set up to clamp level. same as in table 5. d9 is inverted in table 5. d8 to d0 are inverted in table 5. d9 to d0 are inverted in table 5. output code is set up to clamp level. low-power wait state normal operation pre-blanking normal operation pre-blanking test mode table 4 adc output code output pin output codes steps d1 h l l h h l l l h h d0 h l h l h l l h l h d2 l h h h h l h h h h d7 l l l l h l h h h h d5 l l l l h l h h h h d4 l l l l h l h h h h d3 l l l l h l h h h h d6 l l l l h l h h h h d8 l l l l h l h h h h d9 l l l l l h h h h h 3 4 5 6 511 512 1020 1021 1022 1023 table 5 adc output code (test1) d8 l l l l h h l l l l d9 l l l l l h h h h h 3 4 5 6 511 512 1020 1021 1022 1023 d1 h h h l l l h h l l d0 l l h h l l l h h l d2 l h h h l l l l l l d7 l l l l l l l l l l d5 l l l l l l l l l l d4 l l l l l l l l l l d3 l l l l l l l l l l d6 l l l l l l l l l l output pin output codes steps
hd49340np/hnp rev.1.0 apr 20, 2004 page 8 of 21 7. adjustment of black-level s/h response frequency characteristics the cr time constant that is used for sampling/hold (s/h) at the black level can be adjusted by changing the register settings, as shown in table 6. table 6 shsw cr time constant setting l [0] 2.20 nsec (72 mhz) 2.30 nsec (69 mhz) l [1] l [2] l 2.51 nsec (63 mhz) 2.64 nsec (60 mhz) 2.93 nsec (54 mhz) 3.11 nsec (51 mhz) 3.52 nsec (45 mhz) 3.77 nsec (42 mhz) [3] h [0] l [1] l [2] l [3] l [0] h [1] l [2] l [3] h [0] h [1] l [2] l [3] l [0] l [1] h [2] l [3] h [0] l [1] h [2] l [3] l [0] h [1] h [2] l [3] h [0] h [1] h [2] l [3] l [0] shsw-fsel (register setting) 4.40 nsec (36 mhz) 4.80 nsec (33 mhz) l [1] l [2] h cr time constant (typ) (cutoff frequency conversion) 5.87 nsec (27 mhz) 6.60 nsec (24 mhz) 8.80 nsec (18 mhz) 10.6 nsec (15 mhz) 17.6 nsec (9 mhz) 26.4 nsec (6 mhz) [3] h [0] l [1] l [2] h [3] l [0] h [1] l [2] h [3] h [0] h [1] l [2] h [3] l [0] l [1] h [2] h [3] h [0] l [1] h [2] h [3] l [0] h [1] h [2] h [3] h [0] h [1] h [2] h [3] blkc c4 23 the shamp frequency characteristics can be adjusted by changing the register settings and the c4 value of the external 23rd pin. the settings are shown in table 7. values other than those shown in the table 7 cannot be used. 8. shsw-fsel (register setting) cr time constant (typ) (cutoff frequency conversion) table 7 shamp frequency characteristics setting 49 mhz 15000 pf (620 pf) 24 mhz 27000 pf (820 pf) 32 mhz 22000 pf (750 pf) sha-fsel (register setting) lopwr (register setting) note: upper line middle line lower line : shamp cutoff frequency (typ) : standard value of c4 (maximum value is not defined) : minimum value of c4 (do not set below this value) 56 mhz 18000 pf (360 pf) 116 mhz 10000 pf (270 pf) "lo" "hi" 75 mhz 13000 pf (300 pf) h [0] l [1] l [0] h [1] h [0] h [1]
hd49340np/hnp rev.1.0 apr 20, 2004 page 9 of 21 timing chart figure 2 shows the timing chart when cdsin and adcin input modes are used. d0 to d9 d0 to d9 note: the phases of spblk and spsig are those when the serial data spinv bit is set to low. 012 910 11 n+1 n+2 n+9 n+10 n+11 n n ? 9n ? 8n ? 1n cdsin spblk spsig adclk n+2 n+8 n+9 n+10 n+11 n ? 8 n ? 9n ? 1 adcin adclk n n+1 n n+1 n ? 10 ? when cdsin input mode is used ? when adcin input mode is used ~ figure 2 output timing chart when cdsin and adcin input modes are used ? the adc output (d0 to d9) is output at the rising edge of the adclk in both modes. ? pipe-line delay is ten clock cycles when cdsin is used and nine when adcin is used. ? in adcin input mode, the input signal is sampled at the rising edge of the adclk.
hd49340np/hnp rev.1.0 apr 20, 2004 page 10 of 21 detailed timing specifications detailed timing specifications wh en cdsin input mode is used figure 3 shows the detailed timing specifications when the cdsin input mode is used, and table 8 shows each timing specification. black level signal level d0 to d9 cdsin spblk vth (2) (3) spsig adclk (7) vth vth (8) (9) (10) (4) (1) (5) (6) note: 1. when serial data spinv bit is set to low. (when the spinv bit is set to high, the polarities of the spblk and the spsig are inverted.) figure 3 detailed timing chart when cdsin input mode is used table 8 timing specifications when the cdsin input mode is used no. timing symbol min typ max unit (1) black-level signal fetch time t cds1 ? (1.5) ? ns (2) spblk low period * 1 t cds2 typ 0.8 1/4f clk typ 1.2 ns (3) signal-level fetch time t cds3 ? (1.5) ? ns (4) spsig low period * 1 t cds4 typ 0.8 1/4f clk typ 1.2 ns (5) spblk rising to spsig rising time * 1 t cds5 typ 0.85 1/2f clk 0.90 typ 1.00 ns (6) spsig rising to adclk rising inhibition time * 1 t cds6 1 5 9 ns (7), (8) adclk t wh min./t wl min. t cds7, 8 11 ? ? ns (9) adclk rising to digital output hold time t chld9 3 7 ? ns (10) adclk rising to digital output delay time t cod10 ? 16 24 ns note: 1. spblk and spsig polarities when serial data spinv bit is set to low. obp detailed timing specifications figure 4 shows the obp detailed timing specifications. the ob period is from the fifth to the twelfth clock cycle after the ob pulse is input. the average of the black signal level is taken for eight input cycles during the ob period and becomes the clamp level (dc standard). cdsin obp note: ob pulse > 2 clock cycles when serial data obpinv bit is set to low (when the obpinv is set to high, the polarity of the obp is inverted.) ob period * 1 1. shifts 1 clock cycle depending on the obp input timing. n n+1 n+5 n+12 n+13 this edge is used, when obp pulse-width period is clamp-on. figure 4 obp detailed timing specifications
hd49340np/hnp rev.1.0 apr 20, 2004 page 11 of 21 detailed timing specifica tions at pre-blanking figure 5 shows the pre-blanking detailed timing specifications. digital output (d0 to d9) adc data clamp level adc data pblk t pblk adclk 2 clocks adclk 10 clocks (shifts one clock cycle depending on the pblk input timing) when serial data spinv bit is set to low (when the spinv is set to high, the pblk polarity is inverted.) vth v ol v oh figure 5 detailed timing sp ecifications at pre-blanking detailed timing specifications wh en adcin input mode is used figure 6 shows the detailed timing chart when adcin input mode is used, and table 9 shows each timing specification. a dcin (1) a dclk d0 to d9 (2) vth v dd /2 (3) (5) (4) figure 6 detailed timing chart when adcin input mode is used table 9 timing specifications when adcin input mode is used no. timing symbol min typ max unit (1) signal fetch time t adc1 ? (6) ? ns (2), (3) adclk t wh min./t wl min. t adc2, 3 typ 0.85 1/2f adclk typ 1.15 ns (4) adclk rising to digital output hold time t ahld4 10 14.5 ? ns (5) adclk rising to digital output delay time t aod5 ? 23.5 31.5 ns
hd49340np/hnp rev.1.0 apr 20, 2004 page 12 of 21 serial interface specifications resister 0 t su t ho t int 1, 2 f sck 50 ns 50 ns timing specifications 50 ns ? min ? ? ? 5 mhz max latches sdata at sck rising edge data is determined at cs rising edge table 10 serial data function list di 00 (lsb) di 01 low low low resister 4 to 7 * 7 test mode (can not be used) high low low resister 1 resister 2 low low high low to high low to high high resister 3 high low high di 02 di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 (msb) hgstop-hsel [1] hgain-nsel [0] sha-fsel [0] (lsb) sha-fsel [1] (msb) shsw-fsel [0] (lsb) shsw-fsel [1] shsw-fsel [2] shsw-fsel [3] (msb) clamp-level [3] clamp-level [2] clamp-level [1] clamp-level [0] (lsb) c-bias off clamp-level [4] (msb) hgstop-hsel [0] pga gain setting (lsb) pga gain setting pga gain setting pga gain setting pga gain setting pga gain setting output mode setting (test0) pga gain setting pga gain setting (msb) hgain-nsel [1] sck cs sdata di 00 di 01 di 02 di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 t int 1 t ho t su t int 2 f sck figure 7 serial interface timing specifications cannot be used. 0 0 0 1 1 0 low_pwr notes: 1. 2. 3. 4. 5. 6. 7. 8. 2 byte continuous communications. sdata is latched at sck rising edge. insert 16 clocks of sck while cs is low. data is invalid if data transmission is aborted during transmission. the gain conversion table differs in the cdsin input mode and the adcin input mode. stby: reference voltage generator circuit is in the operating state. slp: all circuits are in the sleep state. this bit is used for the ic testing, and cannot be used by the user. the use of this address is prohibited. circuit current and the frequency characteristic are switched. data = 0: 36 mhz guarantee data = 1: 25 mhz guarantee cannot be used. all low cannot be used. all low cannot be used. all low low: cdsin input mode high: cin input mode csel low: normal operation mode high: sleep mode slp low: normal operation mode high: standby mode stby output mode setting (linv) output mode setting (minv) shamp frequency character- istics switching shsw frequency character- istics switching high-speed lead-in cancellation time high-speed lead-in gain multiplication spinv, spsig/spblk/pblk inversion obpinv, obp inversion low: reset mode high: normal operation mode reset gray code [0] (test1) gray code [1] ave_4h cannot be used. gray_test [2] gray_test [0] gray_test [1]
hd49340np/hnp rev.1.0 apr 20, 2004 page 13 of 21 explanation of serial data of cds part serial data of cds part has the following functions. ? pga gain (d5 to d12 of register 0) details are referred to page 5 block diagram. at cds_in mode: ?2.36 db + 0.132 db n (log linear) at adc_in mode: 0.57 times + 0.01784 times n (times linear) ? : full-scale digital output is defined as 0 db when 1 v is input. above pga gain definition means input signal 1 vp-p to cds_in, and set n = 18 (correspond 2.36 db), and then pga outputs the 2 v full-range, and also adc out puts the full code (1023). this mean offset gain of pga has 6 db ? 2.36 db = 3.64 db, therefore it should be decided that how much db add on. (1) level dia explain cds pga 0 db when set n = 18 which correspond to 2.36 db adc (2) level dia on the circuit cds pga 3.64 db + 0.132 db n (cds = 0 db) adc 2 v 1023 (1.0 v) (1.0 v) (2.0 v) (1023) figure 8 level dia of pga ? csel (d15 of register 0) data = 0: select cdsin data = 1: select adcin address std1[7:0] (l) std2[15:8] (h) 1 1 1 1 0 0 0 1 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 sha_fsel test_i2 shsw_fsel test0 minv linv stby slp ? slp and stby (d3, d4 of register 1) slp: stop the all circuit. consumption current of cds part is less than 10 a. start up from offset calibration when recover is needed. stby: only the standard voltage generating circuit is operated. consumption current of cds part is about 3 ma. allow 50 h time for feedback clamp is stabilized until recover. ? output mode (d5 to d7 of register 1 and d4 of register 3) it is a test mode. combination details are table 3 to 5. normally set to all 0. ? sha-fsel (d8 to d9 of register 1) it is a lpf switching of sh amplifier. frequency characteristics are referred to page 8. to get rough idea, set the double cut off frequency point with using. ? shsw-fsel (d10 to d13 of register 1) it is a time constant which sampling the black level of sh amplifier. frequency characteristics are referred to page 8. to get rough idea, set the double cut off frequency point with using. s/n changes by this data, so find the appropriate point with set data to up/down.
hd49340np/hnp rev.1.0 apr 20, 2004 page 14 of 21 ? clamp (d3 to d7 of register 2) determine the ob part level with digital code of adc output. clamp level = setting data 2 + 14 default data is 9 = 32 lsb. ? hgstop-hsel, hgain-nsel (d8 to d11 of register 2) determine the lead-in speed of ob clamp. details are referred to page 6. pga gain need to be changed for switch the high speed leading mode. transfer the gain +1/?1 to previous field, its switch to high speed leading mode. ? low_pwr (d12 of register 2) switch circuit current and frequency characteristic. data = 0: 36 mhz guarantee data = 1: 25 mhz guarantee ? spinv (d13 of register 2) spsig/spblk/pblk input signal inverted switching. data = 1: normal data = 0: inverted ? reset (d15 of register 2) software reset. data = 1: normal data = 0: reset offset calibration should be done when starting up with using this bit. details are referred to page 18. ? c_bias_off (d3 of register 3) center bias is turned off in adcin mode. data = 0: normally on data = 1: off ? ave_4h (d6 of register 3) clamp detection data is averaged 4h. data = 0: 1h data = 1: averaged 4h differential code and gray code (d4 to d5 and d7 to d9 of register 3) ? gray code (d4 to d5 of register 3) dc output code can be change to following type. gray code [1] gray code [0] output code 0 0 binary code 0 1 gray code 1 0 differential encoded binary 1 1 differential encoded gray ? serial data setting items (d7 to d9 of register 3) setting bit setting contents gray_test[0] gray_test[1] standard data output timing control signal (refer to the following table) gray_test[2] adclk polar with obp. (lo positive edge, hi negative edge) ? standard data output timing gray_test[1] gray_test[0] sta ndard data output timing low low third and fourth low high fourth and fifth high low fifth and sixth high high sixth and seventh
hd49340np/hnp rev.1.0 apr 20, 2004 page 15 of 21 ripple (pseudo outline made by quantized error) occurres on the point which swithing the adc output multiple bit in parallel. when switching the several of adc output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. differential code and gray code are recommended for this countermeasure. figure 9 indicates circuit block. when luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function. this function is especially effective for longer the settings of sensor more than clk = 30 khz, and adc output. figure 10 indicates the timing specifications. adc 10 differential sw(d5) carry bit round + ? gray sw(d4) standard data control signal (d9,d8,d7) standard data selector 10-bit output 2clk_dl gray binary conversion figure 9 diff erential code, gray code circuit 1 a dclk obp digital output (beginning edge of obp and standard edge of adclk should be exept 5 ns) (in case of select the positive edge of adclk with d8) (in case of select the positive polar) differential data standard data differential data 2345678910 11 figure 10 differen tial code timing specifications to use differential code, complex circuit is necessary at dsp side. (1) differential coded from adc standard data control signal carry bit round 2clk_dl standard data selector d9 d9 d8 d7 d0 d8 d7 d0 gray binary (2) gray binary conversion figure 11 complex circuit example
hd49340np/hnp rev.1.0 apr 20, 2004 page 16 of 21 absolute maximum ratings (ta = 25 c) item symbol ratings unit power supply voltage v dd (max) 4.1 v analog input voltage v in (max) ?0.3 to av dd +0.3 v digital input voltage v i (max) ?0.3 to dv dd +0.3 v operating temperature topr ?20 to +85 c power dissipation pt(max) 400 mw storage temperature tstg ?55 to +125 c power supply voltage range (hd49340hnp) 2.85 to 3.45 power supply voltage range (hd49340np) vopr 2.70 to 3.45 v notes: 1. v dd indicates av dd and dv dd . 2. av dd and dv dd must be commonly connected outside the ic. when they are separated by a noise filter, the potential difference must be 0.3 v or less at power on, and 0.1 v or less during operation. electrical characteristics (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items common to cdsin and adcin input modes item symbol min typ max unit test conditions remarks v dd hi 2.85 3.00 3.45 v lopwr = low hd49340hnp power supply voltage range v dd low 2.70 3.00 3.45 v lopwr = high hd49340np f clk hi 20 ? 36 mhz lopwr = low hd49340hnp conversion frequency f clk low 5.5 ? 25 mhz lopwr = high hd49340np v ih dv dd 3.0 2.0 ? dv dd v v il 0 ? dv dd 3.0 0.8 v digital input pins other than cs, sck and sdata v ih2 dv dd 3.0 2.25 ? dv dd v digital input voltage v il2 0 ? dv dd 3.0 0.6 v cs, sck, sdata v oh dv dd ?0.5 ? ? v i oh = ?1 ma digital output voltage v ol ? ? 0.5 v i ol = +1 ma i ih ? ? 50 a v ih = 3.3 v digital input current i il ?50 ? ? a v il = 0 v i ozh ? ? 50 a v oh = v dd digital output current i ozl ?50 ? ? a v ol = 0 v adc resolution res 10 10 10 bit adc integral linearity inl ? (3) ? lsbp-p f clk = 25 mhz adc differential linearity+ dnl+ ? 0.3 0.9 lsb f clk = 25 mhz *1 adc differential linearity? dnl? ?0.9 ?0.3 ? lsb f clk = 25 mhz *1 sleep current i slp ?100 0 100 a digital input pin is set to 0 v, output pin is open standby current i stby ? 3 5 ma digital i/o pin is set to 0 v notes: 1. differential linearity is the calculated difference in linearity errors between adjacent codes. 2. values within parentheses ( ) are for reference.
hd49340np/hnp rev.1.0 apr 20, 2004 page 17 of 21 electrical characteristics (cont.) (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items for cdsin input mode item symbol min typ max unit test conditions remarks consumption current (1) i dd1 ? 45.0 54.5 ma f clk = 36 mhz cdsin mode lopwr = low consumption current (2) i dd2 ? 23.5 31.0 ma f clk = 25 mhz cdsin mode lopwr = high ccd offset tolerance range v ccd (?100) ? (100) mv timing specifications (1) t cds1 ? (1.5) ? ns timing specifications (2) t cds2 typ 0.8 1/4f clk typ 1.2 ns timing specifications (3) t cds3 ? (1.5) ? ns timing specifications (4) t cds4 typ 0.8 1/4f clk typ 1.2 ns timing specifications (5) t cds5 typ 0.85 1/2f clk 0.90 typ 1.00 ns timing specifications (6) t cds6 1 5 9 ns timing specifications (7) t cds7 11 ? ? ns timing specifications (8) t cds8 11 ? ? ns timing specifications (9) t chld9 3 7 ? ns timing specifications (10) t cod10 ? 16 24 ns c l = 10 pf see table 8 clp(00) ? (14) ? lsb clp(09) ? (32) ? lsb clamp level clp(31) ? (76) ? lsb pga(0) ?4.4 ?2.4 ?0.4 db pga(63) 4.1 6.1 8.1 db pga(127) 12.5 14.5 16.5 db pga(191) 21.0 23.0 25.0 db pga gain at cds input pga(255) 29.4 31.4 33.4 db note : values within parentheses ( ) are for reference. ? items for adcin input mode item symbol min typ max unit test conditions remarks consumption current (3) i dd3 ? 30.0 38.0 ma f clk = 36 mhz adcin mode lopwr = low consumption current (4) i dd4 ? 17.0 21.5 ma f clk = 25 mhz adcin mode lopwr = high timing specifications (11) t adc1 ? (6) ? ns timing specifications (12) t adc2 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (13) t adc3 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (14) t ahld4 10 14.5 ? ns timing specifications (15) t aod5 ? 23.5 31.5 ns c l = 10 pf see table 9 input current at adc input iin cin ?110 ? 110 a v in = 1.0 v to 2.0 v clamp level at adc input of2 ? (512) ? lsb gsl(0) 0.45 0.57 0.72 times gsl(63) 1.36 1.71 2.16 times gsl(127) 2.27 2.86 3.60 times gsl(191) 3.18 4.00 5.04 times pga gain at adc input gsl(255) 4.08 5.14 6.47 times note : values within parentheses ( ) are for reference.
hd49340np/hnp rev.1.0 apr 20, 2004 page 18 of 21 operation sequence at power on reset bit reset = "low" (reset mode) v dd obp high-speed pulse is the right phase obp is the right phase spblk spsig adclk etc. obp is started within this period hd49340np/hnp serial data transfer reset = "high" (reset cancellation) must be stable within the operating power supply voltage range start control of tg and camera dsp (1) register 2 setting (2) register 2 setting (3) register 0 and 1 settings (4) please perform an offset calibration in the period which avoided pblk of v. : set all bits in register 2 to the usage condition, and set the reset bit to low. : cancel the reset mode by setting the register 2 reset bit to high. do not change other register 2 settings. offset calibration starts automatically. : after the offset calibration is terminated, set registers 0 and 1. (2) register 2 setting (1) register 2 setting (3) registers 0 and 1 settings 0 ms or more 1 ms or more 2 ms or more 2 ms or more prohibition period ends after 40000 clock cycles a utomatic offset calibration the following describes the above serial data transfer. for details on registers 0, 1, and 2, refer to table 10. (4)offset calibration (automatically starts after reset cancellation)
hd49340np/hnp rev.1.0 apr 20, 2004 page 19 of 21 notice for use 1. careful handling is necessary to prevent damage due to static electricity. 2. this product has been developed for consumer applications, and should not be used in non-consumer applications. 3. as this ic is sensitive to power line noise, the ground impedance should be kept as small as possible. also, to prevent latchup, a ceramic capacitor of 0.1 f or more an d an electrolytic capacitor of 10 f or more should be inserted between the ground and power supply. 4. common connection of av dd and dv dd should be made off-chip. if av dd and dv dd are isolated by a noise filter, the phase difference should be 0.3 v or less at power-on and 0.1 v or less during operation. 5. if a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below. hd49340np/hnp av ss dv ss av dd dv dd noise filter a nalog +3.0v hd49340np/hnp dv ss av ss dv dd av dd 100 h 0.01 f noise filter example of noise filte r digital +3.0v 0.01 f 6. connect av ss and dv ss off-chip using a common ground. if there are separate analog system and digital system set grounds, connect to the analog system. 7. when v dd is specified in the data sheet, this indicates av dd and dv dd . 8. no connection (nc) pins are not connected inside the ic , but it is recommended that they be connected to power supply or ground pins or left open to prevent crosstalk in adjacent analog pins. 9. to ensure low thermal resistance of the package, a cu-type lead material is used. as this material is less tolerant of bending than fe-type lead material, careful handling is necessary. 10. the infrared reflow soldering method should be used to mount the chip. note that general heating methods such as solder dipping cannot be used. 11. serial communication should not be performed during the effective video period, since this will result in degraded picture quality. also, use of dedicated ports is recommended for the sck and sdata signals used in the hd49330af. if ports are to be shared with another ic, picture quality should first be thoroughly checked. 12. at power-on, automatic adjustment of the offset voltage generated from pga, adc, etc., must be implemented in accordance with the power-on operating sequence (see page 15).
hd49340np/hnp rev.1.0 apr 20, 2004 page 20 of 21 example of recommended external circuit r11 100 r12 100 r13 100 r10 100 c18 0.1 c19 0.1 c17 0.1 l1 47 ? at cds input notes: 1. for c4, see table 5. 2. for c3, see page 8 "dc offset compensation feedback function". unit: r: ? c: f 17 19 20 21 22 23 24 25 26 c4* 1 c14 0.1 r15 33 k c15 0.1 27 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 18 29 34 35 36 33 32 31 30 28 serial data input gnd from timing generator from ccd out note: external circuit is same as above except for adc input. 3.0 v 3.0 v to camera signal processor c22 0.1 c18 0.1 c19 0.1 c17 0.1 c22 0.1 c1 1 c3 * 2 1 c10 0.1 c10 0.1 c11 0.1 c11 0.1 r15 33 k c16 47/6 c21 47/6 l2 47 r14 100 hd49340np/hnp (cds/pga+adc) l1 47 ? at adc input c15 0.1 serial data input gnd from timing generator to camera signal processor c14 0.1 c2 2.2/16 c16 47/6 c21 47/6 l2 47 hd49340np/hnp (cds/pga+adc) + ? av dd blksh blkfb cdsin blkc bias av dd av ss adcin d9 d8 d7 d6 d5 d4 d3 d2 d1 av ss spsig spblk obp pblk dv dd adclk dv ss drdv dd vrm vrt vrb dv dd dv ss cs sdata sck d0 with adc input 17 19 20 21 22 23 24 25 26 27 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 18 29 34 35 36 33 32 31 30 28 av dd blksh blkfb cdsin blkc bias av dd av ss adcin d9 d8 d7 d6 d5 d4 d3 d2 d1 av ss spsig spblk obp pblk dv dd adclk dv ss drdv dd vrm vrt vrb dv dd dv ss cs sdata sck d0
hd49340np/hnp rev.1.0 apr 20, 2004 page 21 of 21 package dimensions package code jedec jeita mass (reference value) tnp-36 ? ? ? unit: mm 6.20 0.10 0.34 0.11 0.48 0.11 0.27 0.05 19 9 1 27 19 19 27 10 18 10 18 36 28 36 28 6.00 0.05 0.90 0.05 0.22 0.05 6.20 0.10 6.00 0.05 0.22 0.05 0.05 m 0.05 1.00 0.50 1.00 0.50
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